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document id# 081195 date: sep 19, 2007 rev: e version: 2 distribution: public document note: on august 3, 2007, zarlink sem iconductor acquired the products and technology of legerity holdings. ? le7942b subscriber line interface circuit ve580 series distinctive characteristics ? programmable constant-current feed ? receive current gain = 500 ? programmable loop-detect threshold ? low standby power ? performs polarity reversal ? ground-key detector ? pin for external ground-key noise filter capacitor ? test relay driver option ? compatible with le7942 device ? tip open state for ground-start lines ? ?19 v to ?58 v battery operation ? ideal for pbx and kts applications ? on-chip switching regulator for low-power dissipation ? can be used with or without the on-chip switching regulator ? on-hook transmission block diagram vtx vreg vbat 15474a-001 signal transmission input decoder and control ground-key detector ring relay driver test relay driver c1 c2 c3 c4 e1 gkfil rsn off-hook detector power-feed controller ring-trip detector switching regulator testout ringout rd rdc l two-wire a(tip) hpa hpb b(ring) bgnd da db chs chclk vcc vee agnd/dgnd cas det qbat interface a voice solution
le7942b data sheet 2 zarlink semiconductor inc. ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on legerity?s standard military?grade products. valid combinations green package le7942bdjc le7942b?1djc le7942b?2djc non-green package le7942bjc le7942b-1jc LE7942B-2JC le7942b j performance grade blank = standard specification ?1 = performance grading ?2 = performance grading c=commercial (0 c to 70 c)* subscriber line interface circuit c device number/description le7942b d= green package (see note) packaging material blank= standard package plcc package note: the green package meets rohs dir ective 2002/95/ec of the european council to minimize the environmental impact of electrical equipment.
le7942b data sheet 3 zarlink semiconductor inc. connection diagrams top view notes: 1. pin 1 is marked for orientation. 2. tp is a thermal conduction pin tied to substrate (qbat). tp testout l c4 vbat qbat chs chclk e1 ringout bgnd b(ring) a(tip) db gkfil 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 c1 c3 c2 tp agnd/dgnd det da rd hpb hpa vtx vbref rsn cas rdc vreg vcc 32-pin plcc
le7942b data sheet 4 zarlink semiconductor inc. pin descriptions notes: 1. all pins, except chclk, connect to vbat when using slic without a switching regulator. chclk is connected to agnd/ dgnd. 2. to prevent noise pickup by the detectio n circuits when using ground-key detect state (e1 = logical 1), a 3300 pf minimum bypass capacitor is recommended between the gkfil pin and ground. 3. each relay driver has a zener clamp to bgnd. pin names type description agnd/dgnd gnd analog and digital ground. a (tip) output output of a(tip) power amplifier. bgnd gnd battery (power) ground. b (ring) output output of b(ring) power amplifier. c3?c1 input decoder. ttl compatible. c3 is msb and c1 is lsb. c4 input test relay driver command. ttl compatible. a logic low enables the driver. cas capacitor anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation region. chclk input chopper clock. input to switching regul ator (ttl compatible). freq = 256 khz (typ). (see note 1). chs input chopper stabilization. (see note 1) connection for external chopper stabilizing components. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output switchhook detector. when enabled, a logic low indicates the selected detector is tripped. the detector is selected by the logic inputs (c3?c1, e1). the output is open-collector with a built-in 15 k ? pull-up resistor. e1 input ground-key enable. e1 = high connects the ground-key detector to det . e1 = low connects the off-hook or ring-trip detector to det . gkfil ? connection for external ground-key, noise-filter capacitor. (see note 2.) hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. l output (see note 1) switching regulator power transistor. connection point for filter inductor and anode of switching regulator power transistor. connection point for filter inductor and anode of catch diode. has up to 60 v of pulse waveform on it and must be isolated from sensitive circuits. keep the diode connections short because of the high currents and high di/dt. qbat battery quiet battery. (see note 1). filtered battery supply for the signal processing circuits. rd resistor detector resistor. detector threshold set and filter pin. may be connected to ground or -5v. rdc resistor dc feed resistor. connection point for the dc feed current programming network. the other end of the network connects to the receiver summing node (rsn). ringout output ring relay driver. open-collector driver with emitter internally connected to bgnd. (see note 3) rsn input receive summing node. the metallic current (a c and dc) between a(tip) and b(ring) is equal to 500 x the current into this pin. the networks that program receive gain, two-wire impedance, and feed current all connect to this node. testout output test relay driver. open collector driver with emitter internally connected to bgnd. (see note 3) tp thermal thermal pin. connection for heat dissipation. internally connected to substrate (qbat). leave as open circuit or connected to qbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation. vbat battery battery supply. vcc power +5 v power supply. vbref power reference voltage. no current on the pin. may be connected to qbat or ?5 v. vreg input regulated voltage. (see note 1.) provides negative power supply for power amplifiers. connection point for inductor, filter capacitor, and chopper stabilization. vtx output transmit audio. this output is a unity gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
le7942b data sheet 5 zarlink semiconductor inc. absolute maximum ratings storage temperature . . . . . . . . . . . . ?55 c to +150 c v cc with respect to agnd/dgn d . . . ?0.4 v to +7.0 v v ee with respect to agnd/dgnd . . . +0.4 v to qbat v bat with respect to agnd/dgnd. . . +0.4 v to ?70 v note: rise time of v bat (dv/dt) must be limited to 27 v/ s or less when q bat bypass = 0.33 f. bgnd with respect to agnd/dgnd . +1.0 v to ?3.0 v a(tip) or b(ring) to bgnd: continuous . . . . . . . . . . . . . . . . . . ?70 v to +1.0 v 10 ms (f = 0.1 hz) . . . . . . . . . . . . . ?70 v to +5.0 v 1 s (f = 0.1 hz) . . . . . . . . . . . . . . . ?90 v to +10 v 250 ns (f = 0.1 hz) . . . . . . . . . . . . ?120 v to +15 v current from a(ti p) or b(ring) . . . . . . . . . . . . 150 ma voltage on ringout, testout . . . .bgnd to + 7 v voltage on ringout, testout (transient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bgnd to +10 v current through relay drivers . . . . . . . . . . . . . . 60 ma voltage on ring-trip inputs (da and db) . . . . . . . . . . . . . . . . . . . . . v bat to 0 v current into ring-trip inputs . . . . . . . . . . . . . . . . . 10 ma peak current into regulator switch (l pin). . . . . . . . . . . . . . . . . . . . . . . 150 ma switcher transient peak off voltage on l pin. . . . . . . . . . . . . . . . . . . . . . +1.0 v c4?c1, e1, chclk to agnd/dgnd . . . . . . . . . . . .?0.4 v to v cc + 0.4 v maximum power dissipation, t a (see note) . . . . .70 c in 32-pin plcc package. . . . . . . . . . . . . . . 1.74 w note: thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165 c. the device should never be exposed to this temperature. operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations for more information. stresses above those listed un der absolute maximum ratings cancause permanent device failur e. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature . . . . . . . . . . . . . . 0 c to +70 c* v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 v to 5.25 v v ee . . . . . . . . . . . . . . . . . . . . . . . . . . ?4.75 v to qbat v bat . . . . . . . . . . . . . . . . . . . . . . . . . . ?19 v to ?58 v** agnd/dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v bgnd with respect to agnd/dgnd. . . . . . . . . . . . ?100 mv to +100 mv load resistance on vtx to ground . . . . . . 10 k ? min the operating ranges define those limits between which the functionality of the device is guaranteed. *legerity guarantees the perfo rmance of this device over commercial (0 to 70 c) and industrial (-40 to 85 c) temperature ranges by conductin g electrical characterization over each range and by conduc ting a production test with single insertion coupled to periodic sampling. these characterization and test procedures comply with section 4.6.2 of bellcore tr-tsy-000357 component reliability assurance requirements for telecommunications equipment. ** can be used without switching regulator components in this range of battery voltages, provided maximum power dissipation specifications are not exceeded. package assembly the non-green package devices are assembled with industry-standard mold compounds, and the leads possess a tin/lead (sn/pb) plating. these packages are compatible with conventional snpb eutectic solder board assembly processes. the peak soldering temperature should not exceed 225c during printed circuit board assembly. the green package devices are assembled with enhanced environmental compatible lead-free, halogen-free, and antimony-free materials. the leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-free board assembly processes. the peak soldering temperature should not exceed 245c during printed circuit board assembly. refer to ipc/jedec j-std-020b table 5-2 for the recommended solder reflow temperature profile
le7942b data sheet 6 zarlink semiconductor inc. electrical characteristics description test conditions (see note 1) grade min typ max unit note analog (v tx ) output impedance all 3 ? ? 4 analog (v tx ) output offset 0 c to +70 c ?1 ?2 ?35 ?35 ?30 ? +35 +35 +30 mv ? ?40 c to +85 c ?1 ?2 ?40 ?40 ?35 ? +40 +40 +35 4 analog (rsn) input impedance 300 hz to 3.4 khz all ? 1 20 ? ? longitudinal impedance at a or b all ? ? 35 ? overload level 4-wire 2-wire all ?2.5 ? +2.5 vpk 2 transmission performance, 2-wire impedance (see test circuit d) 2-wire return loss 300 to 3400 hz all 26 ? ? db 4, 10 longitudinal balance (2-wire and 4-wire, see test circuit c); r l = 600 ? longitudinal to metallic l-t, l-4 200 hz to 1 khz normal polarity 0 c to +70 c normal polarity ?40 c to +85 c reverse polarity ?1 ?2 ?2 ?2 52 52 63 58 54 ?? db 1, 2 1, 2, 4 1, 2 1 khz to 3.4 khz normal polarity 0 c to +70 c normal polarity ?40 c to +85 c reverse polarity ?1 ?2 ?2 ?2 52 52 58 54 54 ?? 1, 2 1, 2, 4 1, 2 longitudinal signal generation 4-l 300 hz to 800 hz reverse polarity ?1 ?2 40 40 42 ?? longitudinal current capability per wire active state oht state all ? 28 18 ? marms 4 insertion loss (4- to 2-wire, see test circuit b) bat = ?48 v, r ldc = r lac = 600 ? ; bat = ?24 v, r ldc = 300 ? , r lac = 600 ? gain accuracy 0 dbm, 1 khz 0 c to +70 c ?1 ?2 ?0.15 ?0.15 ?0.10 ? +0.15 +0.15 +0.10 db 0 dbm, 1 khz ?40 c to +85 c ?1 ?2 ?0.20 ?0.20 ?0.15 ? +0.20 +0.20 +0.15 4 variation with frequency 300 hz to 3400 hz relative to 1 khz 0 c to +70 c ?1 ?2 ?0.15 ?0.15 ?0.10 ? +0.15 +0.15 +0.10 300 hz to 3400 hz relative to 1 khz ?40 c to +85 c ?1 ?2 ?0.20 ?0.20 ?0.15 ? +0.20 +0.20 +0.15 4
le7942b data sheet 7 zarlink semiconductor inc. gain tracking 0 c to +70 c +7 dbm to ?55 dbm reference: ?0 dbm all ?0.10 ? +0.10 db ?40 c to +85 c +7 dbm to ?55 dbm reference: ?0 dbm all ?0.15 ? +0.15 4 insertion loss and balance return signal (2- to 4-wire and 4- to 4-wire, see test circuits a and b) bat = ?48 v, r ldc = r lac = 600 ? ; bat = ?24 v, r ldc = 300 ? , r lac = 600 ? gain accuracy 0 dbm, 1 khz 0 c to +70 c ?1 ?2 ?6.17 ?6.17 ?6.12 ?6.02 ?5.87 ?5.87 ?5.92 db 3 3 3 0 dbm, 1 khz ?40 c to +85 c ?1 ?2 ?6.22 ?6.22 ?6.17 ?6.02 ?5.82 ?5.82 ?5.87 3, 4 3, 4 3, 4 variation with frequency 300 hz to 3400 hz relative to 1 khz 0 c to +70 c all ?0.10 +0.10 3 300 hz to 3400 hz relative to 1 khz ?40 c to +85 c all ?0.15 +0.15 3, 4 gain tracking 0 c to +70 c +3 dbm to ?55 dbm reference: 0 dbm all ?0.10 +0.10 3 ?40 c to +85 c +3 dbm to ?55 dbm reference: 0 dbm all ?0.15 ?0.15 3, 4 group delay f = 1 khz all 5.3 s4, 12 total harmonic distortion (2- to 4-wire and 4- to 2-wire, see test circuits a and b) bat = ?48 v, r ldc = r lac = 600 ? harmonic distortion 0 dbm all ?64 ?50 db 300 hz to 3400 hz +7 dbm all ?55 ?40 6 idle channel noise bat = ?48 v, r ldc = r lac = 600 ? ; bat = ?24 v, r ldc = 300 ? , r lac = 600 ? c-message weighted noise 2-wire, 0 c to +70 c 2-wire, ?40 c to +85 c all +7 +10 +12 dbmc 4 4 psophometric weighted noise 2-wire, 0 c to +70 c 2-wire, ?40 c to +85 c all ?83 ?80 ?78 dbmp ? 4 single frequency out-of-band noise (see test circuit e) metallic 4 khz to 9 khz 9 khz to 1 mhz 256 khz and harmonics** all ?76 ?76 ?63 dbm 4 4, 5, 8 4, 5 longitudinal 1 khz to 15 khz above 15 khz 256 khz and harmonics** all ?70 ?85 ?57 4 4, 5, 8 4, 5 note: **applies only when switching regulator is used. electrical character istics (continued) description test conditions (see note 1) grade min typ max unit note
le7942b data sheet 8 zarlink semiconductor inc. line characteristics (see figures 1a, 1b, 1c) short loops, active state v bat = ?24 v, r ldc = 300 ? v bat = ?43 v, r ldc = 600 ? v bat = ?48 v, r ldc = 600 ? all 31.8 34.4 37.0 ma 4, 9 4 ? long loops, active state v bat = ?24 v, r ldc = 640 ? v bat = ?43 v, r ldc = 1300 ? v bat = ?48 v, r ldc = 1900 ? all 20.0 23.0 18.0 4, 9 4 ? oht state v bat = ?24 v, r ldc = 300 ? v bat = ?48 v, r ldc = 600 ? all 31.4 34.4 37.4 4, 9 ? loop current tip open state, r l = 0 ? disconnect state, r l = 0 ? all 1.0 i l lim (i tip and i ring ) tip and ring shorted to gnd all 70 120 power dissipation battery, normal loop polarity on-hook open circuit state v bat = ?24 v, w/o switching reg. v bat = ?48 v, with switching reg. all 30 35 75 100 mw 9 ? on-hook oht state v bat = ?24 v, w/o switching reg. v bat = ?48 v, with switching reg. all 80 130 225 9 ? on-hook active state v bat = ?24 v, w/o switching reg. v bat = ?48 v, with switching reg. all 80 130 225 300 9 ? off-hook oht state r l = 50 ? v bat = ?24 v, w/o switching reg. v bat = ?48 v, with switching reg. all 500 400 950 750 9 ? off-hook active state r l = 50 ? v bat = ?24 v, w/o switching reg. v bat = ?48 v, with switching reg. all 800 450 1100 1000 9 ? supply currents, battery = ?24 v or ?48 v v cc on-hook supply current open circuit state oht state active state all 2.5 4.5 4.5 4.5 10.0 12.0 ma 9 v bref on-hook supply current open circuit state oht state active state all 0 0 0 v bat on-hook supply current open circuit state oht state active state all 0.6 2.3 2.3 1.0 5.0 6.0 power supply rejection ratio (v ripple = 50 mvrms) v cc 50 hz to 3.4 khz 3.4 khz to 50 khz all 25 22 45 35 db 6 v bat 50 hz to 3.4 khz 3.4 khz to 50 khz all 27 20 45 40 effective int. resistance cas to gnd all 85 170 255 k ? 4 off-hook detector current threshold i det = 365/r d if r d to gnd i det = 1825/r d if r d to ?5v all ?20 +20 % electrical character istics (continued) description test conditions (see note 1) grade min typ max unit note
le7942b data sheet 9 zarlink semiconductor inc. ground-key detector thresholds, active state ground-key resistance threshold v bat = ?24 v, b(ring) to gnd v bat = ?48 v, b(ring) to gnd all 1.0 2.0 2.2 5.0 4.5 10.0 k ? 9 ? ground-key current threshold b(ring) to gnd midpoint to gnd all 9 9 ma 7 effective internal resistance gkfil to agnd/dgnd all 18 36 54 k ? 4 ring-trip detector input bias current all ?5 ?0.05 a offset voltage source resistance = 0 to 2 m ? all ?50 0 +50 mv 11 logic inputs (c4?c1, e1, and chclk) input high voltage all 2.0 v input low voltage all 0.8 input high current all inputs except e1 all ?75 40 a input high current input e1 all ?75 45 input low current all ?0.4 ma logic output (det ) output low voltage i out = 0.3 ma all 0.4 v output high voltage i out = ?0.1 ma all 2.4 relay driver outputs (ringout, testout) on voltage 25 ma sink all 0.3 +1.5 v off leakage v oh = 5 v all 100 a zener break-over i l = 100 a all 6 7.2 v zener on voltage i l = 30 ma all 8 electrical character istics (continued) description test conditions (see note 1) grade min typ max unit note
le7942b data sheet 10 zarlink semiconductor inc. relay driver schematics switching characteristics switching waveforms symbol parameter test conditions temperature range min typ max unit note tgkde e1 low to det high (e0 = 1) e1 low to det low (e0 = 1) ground-key detect state r l open, r g connected (see figure h) 0 c to +70 c ?40 c to +85 c 0 c to +70 c ?40 c to +85 c 3.8 4.0 1.1 1.6 s4 tshde e1 high to det low (e0 = 1) e1 high to det high (e0 = 1) switchhook detect state r l = 600 ? , r g open (see figure g) 0 c to +70 c ?40 c to +85 c 0 c to +70 c ?40 c to +85 c 1.2 1.7 3.8 4.0 ringout bgnd testout bgnd det tgkde tshde tgkde tshde e1 e1 to det 15474a-003 note: all delays measured at 1.4 v levels.
le7942b data sheet 11 zarlink semiconductor inc. notes: 1. unless otherwise noted, test conditions are bat = ?48 v, v cc = +5 v, r l = 600 ? , c hp = 0.33 f, r dc1 = r dc2 = 9.09 k ? , c dc = 0.39 f, r d = 35.4 k ? when r d is connected to ground and r d = 177 k ? when rd is con- nected to -5v. c cas = 0.47 f, no fuse resistors, r t =150 k ? , and r rx = 150 k ? . switching regulator components: l = 1 mh, c fil = 0.47 f (see application circuit). 2. overload level is defined when thd = 1%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes the two-wire ac load impedance matches the programmed impedance. 4. not tested in production. this parameter is guarant eed by characterization or correlation to other tests. 5. for frequencies below 12 khz, these tests are performed with a longitudinal impedance of 90 ? and metallic impedance of 300 ? . for frequencies greater than 12 khz, a longitudinal impedance of 90 ? and a metallic impedance of 135 ? is used. these tests are extremely sensitive to circuit board layout. please refer to application notes for details. 6. this parameter is tested at 1 khz in production. performanc e at other frequencies is g uaranteed by characterization. 7. ?midpoint? is defined as the connection point between two 300 ? series resistors connected between a(tip) and b(ring). 8. fundamental and harmonics from 256 khz switch regulator chopper are not included. 9. for ?24 v battery, switching regulator is disabled. l, chs, and vreg pins connected to vbat pin; chclk pin connected to agnd/dgnd. 10. assumes the following z t network: 11. tested with 0 ? source impedance. 2 m ? is specified for system design purposes only. 12. group delay can be considerably reduced by using a z t network such as that shown in note 10 above. the network reduces the group delay to less than 2 s. the effect of group delay on linecard perfo rmance may be compensated for by using the qslac? or dslac? device. vtx rsn 75 k ? 75 k ? 120 pf table 1. slic device decoding det output state c3 c2 c1 two-wire status e1 = 0 e1 = 1 0 0 0 0 open circuit ring trip ring trip 1 0 0 1 ringing ring trip ring trip 2 0 1 0 active loop detector ground key 3 0 1 1 on-hook tx (oht) loop detector ground key 4 1 0 0 tip open loop detector ? 5 1 0 1 reserved loop detector ? 6 1 1 0 active polarity reversal loop detector ground key 7 1 1 1 oht polarity reversal loop detector ground key table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse re- sistors are r f , and z 2win is the desired 2-wire ac input im- pedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z t 250 z 2win 2r f ? ? () =
le7942b data sheet 12 zarlink semiconductor inc. note: *r fuse = 20 ? 50 ? , user selectable. z rx is connected from v rx to the r sn . z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. r dc1 and r dc2 are approximately equal. i loop is the desired loop current in the constant-current region. if r d is connected to ground. if r d is connected to -5v. r d and c d form a network connected from rd to either ground or ?5 v, and i t is the threshold current between on hook and off hook. c cas is the regulator filter capacitor, and f c is the desired filter cut-off frequency. table 2. user-programmable components z rx z l g42 l ------------- 500z t z t 250 z l 2r f + () + ------------------------------------------------- - ? = r dc1 r dc2 625 i loop ------------- - = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ------------------------------- - ? = r d 365 i t -------- - = r d 1825 i t ----------- - = c d 0.5 ms r d ---------------- - = c cas 1 3.4 10 5 f c ? ----------------------------- =
le7942b data sheet 13 zarlink semiconductor inc. dc feed characteristics r dc1 + r dc2 = r dc = 18.18 k ? active state oht state notes: 1. constant-current region: active state: oht state: 2. anti-saturation 2 region: active state: and oht state: i l 625 r dc ---------- - = i l 625 r dc --------- - = v ab bat 7.9 ? i l r dc 210 ---------- - ?? ?? ? = a. v a ?v b (v ab ) voltage vs. loop current (typical) vab vesus iloop, bat =-48v 0 5 10 15 20 25 30 35 40 45 1 4 7 10 13 16 19 22 25 28 31 34 37 iloop vab 7942b 7942 (active) 7942 (oht)
le7942b data sheet 14 zarlink semiconductor inc. dc feed characteristics (continued) b. loop current vs. load resistance (typical) r dc1 + r dc2 = r dc = 18.18 k ? iloop vesus loop resistance, bat = -48v 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 1 5 9 13 17 21 25 29 33 37 iloop loop resistance 7942b 7942 (active) feed current programmed by r dc1 and r dc2 15474a-004 a b r l i l a b r dc1 r dc2 rdc c dc slic c. feed programming figure 1. dc feed characteristics rsn
le7942b data sheet 15 zarlink semiconductor inc. test circuits vtx rsn agnd r t r rx r l 2 v l v ab v ab r l rsn agnd vtx v rx r rx i l2-4 = ?20 log (v tx / v ab ) a. two- to four-wire insertion loss i l4-2 = ?20 log (v ab / v rx ) b. four- to two-wire insertion loss and balance return signal vtx rsn agnd r t r rx vrx s2 open, s1 closed: brs = 20 log (v tx / v rx ) slic slic slic slic r l 2 b (ring) a (tip) b (ring) a (tip) r l 2 r l 2 v l s1 v l b (ring) a (tip) s2 1/ c << r l c l-t long. bal. = 20 log (v ab / v l ) l-4 long. bal. = 20 log (v tx / v l ) s2 closed, s1 open: 4-l long. sig. gen. = 20 log (v l / v rx ) c. longitudinal balance r r v m z in z d v s r t r rx b(ring) a (tip) rsn agnd vtx d. two-wire return loss test circuit note: z d is the desired impedance (e.g., the characteristic impedance of the line). r l = ?20 log (2 v m / v s ) r t
le7942b data sheet 16 zarlink semiconductor inc. test circuits (continued) 1/ c << 90 ? e. single-fre quency noise slic b(ring) a(tip) 68 ? 68 ? 56 ? c c v n idc s m r l r l r e s e a(tip) b(ring) current feed or ground key f. ground-key detection center point test v cc 6.2 k ? 15 pf e1 a(tip) b(ring) g. loop-detector switching r l = 600 ? h. ground-key switching r g det r g : 2 k ? at v bat = ?48 v 1 k ? at v bat = ?24 v a(tip) b(ring)
le7942b data sheet 17 zarlink semiconductor inc. physical dimensions 32-pin plcc notes: 1 dimensioning and tolerancing conform to asme y14,5m-1994. 2 to be measured at seating plan - c - contact point. 3 dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.010 inch per side. dimensions d and e include mold mismatch and determined at the parting line; that is d1 and e1 are measured at the extreme material condition at the upper or lower parting line. 4 exact shape of this feature is optional. 5 details of pin 1 identifier are optional but must be located within the zone indicated. 6 sum of dam bar protrusions to be 0.007 max per lead. 7 controlling dimension : inch. 8 reference document : jedec ms-016 32-pin plcc jedec # ms-016 s y mbol min nom max a 0.125 -- 0.140 a1 0.075 0.090 0.095 d 0.485 0.490 0.495 d1 0.447 0.450 0.453 d2 e 0.585 0.590 0.595 e1 0.547 0.550 0.553 e2 & 0 deg -- 10 deg 32-pin plcc 0.205 ref 0.255 ref note: packages may have mold tooling markings on the surface. these markings have no impact on th e form, fit or function of the device. markings will vary with the mold tool used in manufacturing.
le7942b data sheet 18 zarlink semiconductor inc. revision history revision a1 to b1 ? page 12, modified zrx equation. revision b1 to c1 ? page 8, line characteristics, oht state, v bat = ?24 v, r ldc = 600 ? to r ldc = 300 ?. ? page 8, power dissipation, off-hook oht state r l = 50 ?, v bat = ?24 v, w/o switching reg., max 800mw to 950mw. revision c1 to d1 ? page 8, line characteristics, i l lim (i tip and i ring ), changed max value from 105 to 120 . revision d1 to e1 ? added green package opn ? added package assembly section revision e1 to e2 ? enhanced format of package drawing in physical dimensions section ? added new headers/footers due to zarlink purchase of legerity on august 3, 2007
information relating to products and services furnished herein by zarlink semiconductor inc. trading as zarlink semiconductor o r its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual propert y rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of produc t or service conveys any licen se, either express or implied, under patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchaser s of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellectual property rights owned by zarlink. this publication is issued to provide information only and (unl ess agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without not ice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a s pecific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materi als are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl, the zarlink semiconductor logo are trademarks, and legerity, the legerity logo and combinations thereof are regist ered trademarks of zarlink semiconductor inc. all other trademarks and registered tr ademarks are the property of their respective owners. ? 2007 zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at: www.zarlink.com ?

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